1. Field of the Invention
This invention generally relates to digital communications and, more particularly, to a system and method for synchronously transporting Plesiochronous Digital Hierarchy tributaries.
2. Description of the Related Art
Plesiochronous Digital Hierarchy (PDH) was developed by ITU-T G.702 to increase transmission bandwidth by multiplexing primary 2.048 megabyte per second (Mb/s) trunks. The multiplexed trunks are synchronized by adding (stuffing) bits at each level of multiplexing. Bit stuffing is necessary because of timing asynchronicity. The added bits permit multiple trunks to be synchronized without delays, even if one of the trunks is late in delivering data. If one trunk is late in delivering data, the multiplexer substitutes a stuff bit for the late-arriving data bit, and moves on to the following trunk. A 2.048 Mb/s trunk is called E1, and the hierarchy is based on multiples of 4 E1s, as follows:
E2: 4×E1−8 Mb/s;
E3: 4×E2−34 Mb/s;
E4: 4×E3−140 Mb/s; and,
E5: 4×E4−565 Mb/s.
DS1 is a 1.544 Mb/s trunk, which can also be arranged in a hierarchical order in multiples (DS2/DS3/DS4/DS5), similar to the E1 hierarchy (E2/E3/E4/E5). To aid in the synchronization of tributaries, extra justification) bits are added. These justification bits are used to communicate with the multiplexers, providing a map of data and spare (stuffed) bits.
FIG. 1 is a diagram depicting a PDH system for multiplexing and demultiplexing of tributaries (prior art). A multiplexer on one level of the hierarchy adds the spare bits needed for synchronization on that level. Likewise, a demultiplexer removes the spare bits added for that hierarchy level. A multiplexer (MUX) on one level operates on a different timing than multiplexers on another level. That is, the timing for a MUX that combines 30×64 Kb/s channels into on 2.048 Mb/s E1 channel, is necessarily different that the timing for a MUX that combines up to 4×2 Mb/s into 8 Mb/s.
The use of stuff bits points to the basic inflexibility associated with PDH communications. In contrast, Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET), provide for flexible bandwidth on demand capabilities. One advantage of SDH/SONET is that different bandwidth data streams may be interfaced without multiplexing. Like PDH, SDH and SONET may be formed from multiples of E1 (DS1), as follows:
STM-1: 63×E1−155 Mb/s;
STM-4: 4×STM-1−622 Mb/s; and,
STM-16: 4×STM-4−2.5 Gb/s.
PDH may be interfaced with SDH/SONET. To that end, three G transmission series are recommended: G.707—SDH Bit Rates; G.708—The SDH Network Node Interface; and, G.709—Synchronous Multiplexing structure.
FIG. 2 is a diagram depicting the transport of PDH tributaries in a SDH frame (prior art). Except for the 8 Mb/s tributaries, PDH outputs are initially mapped into Containers (C) and then into fixed size Virtual Containers (VC). When the VC is aligned in the Tributary Unit (TU), a pointer is added to indicate the phase of the VC. TU's are then grouped, via Time Division Multiplexing (TDM), into Tributary Unit Groups (TUG). The TUGs are collated into Administrative Units (AU). The VCs and the pointers are incorporated into the section overhead of the STM frame. One AU-4 forms an STM-1, 4 AU-4s form an STM-4. STM-16 and STM-64 are also possible.
FIG. 3 is a diagram depicting a 2 Mb/s E1 tributary mapped into an SDH TU-12 SPE virtual container (prior art). A multiplexer compensates for variations in the speed of the tributary by using stuff bits. Stuff opportunities are identified by S1 and S2, and controlled by the control bits C1 and C2, respectively. A “0” value C bit means that the corresponding S bit is data, and a “1” bit means that the S bit is undefined. O represents overhead channel bits and I represents information bits. The bytes are organized from left to right and top to bottom. The first byte is Path Overhead (POH). The POH uses Bit Interleaved Parity (BIP) to monitor errors. In addition, there are fault indicators, Far End Block Error (FEBE), Remote Fail Indicator (RFI) and Far End Receive Failure (FERF). The Signal Label is set at 2 in this case, to indicate asynchronous data.
FIG. 4 is a diagram depicting a 1.544 Mb/s DSI tributary mapped into a SDH TU-11 SPE virtual container (prior art).
FIG. 5 is a diagram depicting the mapping of TU-11 into a TUG-2 (prior art). A pointer is added to define the phase alignment, by pointing at the POH of each VC. The phase may change during transmission due to a clock domain change between SONET/SDH network elements, introduced by the regeneration and multiplexing equipment, and wander, resulting from temperature differences within the transmission media. Since the various multiplexers may not be synchronous, a pointer is added at a fixed position within the TU. The value of the pointer indicates the start of the VC. The phase of the VC is represented by the pointer, indicating a data rate that is either faster or slower than the TU rate. This difference in speed can be up to one byte per frame in SDH. The TUs are multiplexed into a TUG by interleaving bytes from each TU in turn. Seven TUG 2s can be byte interleaved into a TUG 3, and three TUG 3s can be byte interleaved to form a VC4.
There are other methods for carrying PDH tributaries, although the SONET/SDH is probably the most widely known. These other methods include FTI-2 (Flexible Tributary Interface—level 2), an interface developed by Applied Micro Circuits Corp, which supports both serial and parallel modes of data transfer. Telecom buses are also known that use a parallel bus data format to transport PDH tributaries. SBI (Scalable Bandwidth Interface) is a proprietary interface developed by PMC-Sierra. All these formats support VT bit asynchronous mapping for DS1/E1s tributaries.
It would be advantageous to smoothly transport bit-mapped PDH tributaries (DS1/E1) between Integrated Circuits (ICs) or Telecommunications systems while preserving their payload integrity, timing and synchronization characteristics, and bit sequence order.